TJA1021 Datasheet by NXP USA Inc.

View All Related Products | Download PDF Datasheet
1. General description
The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave
protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle
sub-networks using baud rates from 1 kBd up to 20 kBd (/20 variant) and is compliant with
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V). The
TJA1021 is pin-to-pin compatible with the TJA1020 and MC33662(B).
The transmit data stream of the protocol controller at the transmit data input (TXD) is
converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to
minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an
internal termination resistor. For a master application, an external resistor in series with a
diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects
the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller.
In Sleep mode, the power consumption of the TJA1021 is very low. In failure modes, the
power consumption is reduced to a minimum.
2. Features and benefits
2.1 General
LIN 2.x/ISO 17987-4:2016 (12 V)/SAE J2602 compliant
Baud rate up to 20 kBd (/20 variant)
Very low ElectroMagnetic Emission (EME)
High ElectroMagnetic Immunity (EMI)
Passive behavior in unpowered state
Input levels compatible with 3.3 V and 5 V devices
Integrated termination resistor for LIN slave applications
Wake-up source recognition (local or remote)
K-line compatible
Pin-to-pin compatible with TJA1020 and MC33662(B)
Available in SO8 and HVSON8 packages
Leadless HVSON8 package (3.0 mm × 3.0 mm) with low thermal resistance
supporting Automated Optical Inspection (AOI) capability
2.2 Low power management
Very low current consumption in Sleep mode with local and remote wake-up
TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
Rev. 8 — 18 December 2018 Product data sheet
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 2 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
2.3 Protection mechanisms
High ESD robustness: 6 kV according to IEC 61000-4-2 for pins LIN, VBAT and
WAKE_N
Transmit data (TXD) dominant time-out function
Bus terminal and battery pin protected against transients in the automotive
environment (ISO 7637)
Bus terminal short-circuit proof to battery and ground
Thermally protected
3. Quick reference data
4. Ordering information
[1] TJA1021T/10 and TJA1021TK/10: for the low slope version that supports baud rates up to 10.4 kBd (SAE J2602);
TJA1021T/20 and TJA1021TK/20: for the normal slope version that supports baud rates up to 20 kBd.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VBAT battery supply voltage limiting value with respect to GND 0.3 - +40 V
IBAT battery supply current Sleep mode; VLIN =V
BAT;V
WAKE_N =V
BAT
VTXD = 0 V; VSLP_N = 0 V
2710A
Standby mode; bus recessive
VINH =V
BAT;V
LIN = VBAT; VWAKE_N =V
BAT
VTXD = 0 V; VSLP_N = 0 V
150 450 1000 A
Standby mode; bus dominant
VBAT = 12 V; VINH = 12 V; VLIN = 0 V
VWAKE_N =12V; V
TXD = 0 V; VSLP_N = 0 V
300 800 1200 A
Normal mode; bus recessive
VINH = VBAT; VLIN = VBAT; VWAKE_N =V
BAT
VTXD =5V;V
SLP_N = 5 V
300 800 1600 A
Normal mode; bus dominant
VBAT =12V;V
INH = 12 V; VWAKE_N =12V
VTXD = 0 V; VSLP_N = 5 V
124mA
VLIN voltage on pin LIN limiting value with respect to GND, VBAT and
VWAKE_N
40 - +40 V
Tvj virtual junction temperature limiting value 40 - +150 C
Table 2. Ordering information
Type number[1] Package
Name Description Version
TJA1021T/10
TJA1021T/20
SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TJA1021TK/10
TJA1021TK/20
HVSON8 plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 3 0.85 mm
SOT782-1
001355055
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 3 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
5. Block diagram
Fig 1. Block diagram
FILTER
RXD/
INT
BUS
TIMER
CONTROL
TJA1021
WAKE-UP
TIMER
WAKE_N
VBAT
SLP_N
TXD
RXD
INH
LIN
GND
001aae066
SLEEP/
NORMAL
TIMER
7
3
2
4
1
6
5
8
TEMPERATURE
PROTECTION
TXD
TIME-OUT
TIMER
@fl@@ DEED AT 3333 CECE
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 4 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] For enhanced thermal and electrical performance, solder the exposed center pad of the HVSON8 package
to board ground.
a. TJA1021T/10; TJA1021T/20: SO8 b. TJA1021TK/10; TJA1021TK/20:
HVSON8
Fig 2. Pin configuration diagrams
TJA1021T
RXD INH
SLP_N V
BAT
WAKE_N LIN
TXD GND
015aaa231
1
2
3
4
6
5
8
7
TXD 4
WAKE_N 3
SLP_N 2
RXD 1
GND
5
LIN
6
VBAT
7
INH
8
aaa-032606
TJA1021TK
terminal 1
index area
Transparent top view
Table 3. Pin description
Symbol Pin Description
RXD 1 receive data output (open-drain); active LOW after a wake-up event
SLP_N 2 sleep control input (active LOW); controls inhibit output; resets
wake-up source flag on TXD and wake-up request on RXD
WAKE_N 3 local wake-up input (active LOW); negative edge triggered
TXD 4 transmit data input; active LOW output after a local wake-up event
GND 5[1] ground
LIN 6 LIN bus line input/output
VBAT 7 battery supply voltage
INH 8 battery related inhibit output for controlling an external voltage
regulator; active HIGH after a wake-up event
). Figure 3 local wake-up,
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 5 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
7. Functional description
The TJA1021 is the interface between the LIN master/slave protocol controller and the
physical bus in a Local Interconnect Network (LIN). The TJA1021 is LIN 2.0, LIN 2.1,
LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V) compliant and provides
optimum ElectroMagnetic Compatibility (EMC) performance due to wave shaping of the
LIN output.
The LIN physical layer is independent of higher OSI model layers (e.g., the LIN protocol).
Consequently, nodes containing an ISO 17987-compliant physical layer can be combined,
without restriction, with LIN physical layer nodes that comply with earlier revisions
(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A).
The TJA1021T/20 and TJA1021TK/20 are optimized for the maximum specified LIN
transmission speed of 20 kBd; the TJA1021T/10 and TJA1021TK/10 are optimized for the
LIN transmission speed of 10.4 kBd as specified by the SAE J2602.
7.1 Operating modes
The TJA1021 supports modes for normal operation (Normal mode), power-up (Power-on
mode) and very-low-power operation (Sleep mode). An intermediate wake-up mode
between Sleep and Normal modes is also supported (Standby mode). Figure 3 shows the
state diagram.
[1] Standby mode is entered automatically upon any local or remote wake-up event during Sleep mode. Pin INH and the 30 k termination
resistor at pin LIN are switched on.
[2] The internal wake-up source flag (set if a local wake-up did occur and fed to pin TXD) will be reset after a positive edge on pin SLP_N.
[3] The wake-up interrupt (on pin RXD) is released after a positive edge on pin SLP_N.
[4] Normal mode is entered after a positive edge on SLP_N. As long as TXD is LOW, the transmitter is off. In the event of a short-circuit to
ground on pin TXD, the transmitter will be disabled.
[5] Power-on mode is entered after switching on VBAT.
Table 4. Operating modes
Mode SLP_N TXD (output) RXD INH Transmitter Remarks
Sleep mode 0 weak pull-down floating floating off no wake-up request
detected
Standby[1]
mode
0 weak pull-down if
remote wake-up;
strong pull-down if
local wake-up[2]
LOW[3] HIGH off wake-up request
detected; in this mode
the microcontroller
can read the wake-up
source: remote or
local wake-up
Normal mode 1 HIGH: recessive state
LOW: dominant state
HIGH: recessive state
LOW: dominant state
HIGH Normal mode [2][3][4]
Power-on mode 0 weak pull-down floating HIGH off [5]
Power-on INH. mgr. TERM : 30 m RXDJhamg TXD weak pulmown Transmmer an Normal INH mgr. TERM : so kn RXD recewe dam umpm TxD vansmmam mm Transmmer. on Standby Sleep \NH floatmg \NH, high TERM: high ohmic TERM an m RXD fluahng RXD \uw TxD wake source ampm TransmMer cm TXD, weak puHrdawn Transmuner, on 001332073
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 6 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
7.2 Sleep mode
This mode is the most power-saving mode of the TJA1021. Despite its extreme low
current consumption, the TJA1021 can still be woken up remotely via pin LIN, or woken
up locally via pin WAKE_N, or activated directly via pin SLP_N. Filters at the inputs of the
receiver (LIN), of pin WAKE_N and of pin SLP_N prevent unwanted wake-up events due
to automotive transients or EMI. All wake-up events must be maintained for a certain time
period (twake(dom)LIN, twake(dom)WAKE_N and tgotonorm).
Sleep mode is initiated by a falling edge on pin SLP_N in Normal mode. To enter Sleep
mode successfully (INH becomes floating), the sleep command (pin SLP_N = LOW) must
be maintained for at least tgotosleep.
In Sleep mode the internal slave termination between pins LIN and VBAT is disabled to
minimize the power dissipation in the event that pin LIN is short-circuited to ground. Only
a weak pull-up between pins LIN and VBAT is present.
Sleep mode can be activated independently from the actual level on pin LIN, pin TXD or
pin WAKE_N. This guarantees that the lowest power consumption is achievable even in
case of a continuous dominant level on pin LIN or a continuous LOW on pin WAKE_N.
TERM.: slave termination resistor, connected between pins LIN and VBAT.
Fig 3. State diagram
001aae073
t(SLP_N = 1) > tgotonorm
t(SLP_N = 1) > tgotonorm
t(SLP_N = 1) > tgotonorm
t(SLP_N = 0) > tgotosleep
t(WAKE_N = 0; after 1→0) > tWAKE_N
or t(LIN = 0→1; after LIN = 0) > tBUS
switching on VBAT
Normal
INH: high
TERM. = 30 kΩ
RXD: receive data output
TXD: transmit data input
Transmitter: on
Standby
INH: high
TERM. = 30 kΩ
RXD: low
TXD: wake source output
Transmitter: off
Sleep
INH: floating
TERM. = high ohmic
RXD: floating
TXD: weak pull-down
Transmitter: off
Power-on
INH: high
TERM. = 30 kΩ
RXD: floating
TXD: weak pull-down
Transmitter: off
e Figure 1 Figure 7
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 7 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
When VBAT drops below the power-on-reset threshold Vth(POR)L, the TJA1021 enters
Sleep mode.
7.3 Standby mode
Standby mode is entered automatically whenever a local or remote wake-up occurs while
the TJA1021 is in Sleep mode. These wake-up events activate pin INH and enable the
slave termination resistor at the pin LIN. As a result of the HIGH condition on pin INH the
voltage regulator and the microcontroller can be activated.
Standby mode is signalled by a LOW-level on pin RXD which can be used as an interrupt
for the microcontroller.
In Standby mode (pin SLP_N is still LOW), the condition of pin TXD (weak pull-down or
strong pull-down) indicates the wake-up source: weak pull-down for a remote wake-up
request and strong pull-down for a local wake-up request.
Setting pin SLP_N HIGH during Standby mode results in the following events:
•An immediate reset of the wake-up source flag; thus releasing the possible strong
pull-down at pin TXD before the actual mode change (after tgotonorm) is performed
•A change into Normal mode if the HIGH level on pin SLP_N has been maintained for
a certain time period (tgotonorm)
•An immediate reset of the wake-up request signal on pin RXD
7.4 Normal mode
In Normal mode the TJA1021 is able to transmit and receive data via the LIN bus line. The
receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to
the microcontroller (see Figure 1): HIGH at a recessive level and LOW at a dominant level
on the bus. The receiver has a supply-voltage related threshold with hysteresis and an
integrated filter to suppress bus line noise. The transmit data stream of the protocol
controller at the TXD input is converted by the transmitter into a bus signal with optimized
slew rate and wave shaping to minimize EME. The LIN bus output pin is pulled HIGH via
an internal slave termination resistor. For a master application an external resistor in
series with a diode should be connected between pin INH or VBAT on one side and pin LIN
on the other side (see Figure 7).
When in Sleep, Standby or Power-up mode, the TJA1021 enters Normal mode whenever
a HIGH level on pin SLP_N is maintained for a time of at least tgotonorm.
The TJA1021 switches to Sleep mode in case of a LOW-level on pin SLP_N, maintained
for a time of at least tgotosleep.
7.5 Wake-up
When VBAT exceeds the power-on-reset threshold voltage Vth(POR)H, the TJA1021 enters
Power-on mode. Though the TJA1021 is powered-up and INH is HIGH, both the
transmitter and receiver are still inactive. If SLP_N = 1 for t > tgotonorm, the TJA1021 enters
Normal mode.
There are three ways to wake-up a TJA1021 which is in Sleep mode:
1. Remote wake-up via a dominant bus state of at least twake(dom)LIN
6 Figure 4
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 8 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
2. Local wake-up via a negative edge at pin WAKE_N
3. Mode change (pin SLP_N is HIGH) from Sleep mode to Normal mode
7.6 Remote and local wake-up
A falling edge at pin LIN followed by a LOW level maintained for a certain time period
(twake(dom)LIN) and a rising edge at pin LIN respectively (see Figure 4) results in a remote
wake-up. It should be noted that the time period twake(dom)LIN is measured either in Normal
mode while TXD is HIGH, or in Sleep mode irrespective of the status of pin TXD.
A falling edge at pin WAKE_N followed by a LOW level maintained for a certain time
period (twake(dom)WAKE_N) results in a local wake-up. The pin WAKE_N provides an internal
pull-up towards pin VBAT. In order to prevent EMI issues, it is recommended to connect an
unused pin WAKE_N to pin VBAT.
After a local or remote wake-up, pin INH is activated (it goes HIGH) and the internal slave
termination resistor is switched on. The wake-up request is indicated by a LOW active
wake-up request signal on pin RXD to interrupt the microcontroller.
7.7 Wake-up via mode transition
It is also possible to set pin INH HIGH with a mode transition towards Normal mode via pin
SLP_N. This is useful for applications with a continuously powered microcontroller.
7.8 Wake-up source recognition
The TJA1021 can distinguish between a local wake-up request on pin WAKE_N and a
remote wake-up request via a dominant bus state. 'A local wake-up request sets the
wake-up source flag. The wake-up source can be read on pin TXD in the Standby mode. If
an external pull-up resistor on pin TXD to the power supply voltage of the microcontroller
has been added, a HIGH level indicates a remote wake-up request (weak pull-down at pin
TXD) and a LOW level indicates a local wake-up request (strong pull-down at pin TXD;
much stronger than the external pull-up resistor).
The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag
(signalled on pin TXD) are reset immediately after the microcontroller sets pin SLP_N
HIGH.
7.9 TXD dominant time-out function
A TXD dominant time-out timer circuit prevents the bus line from being driven to a
permanent dominant state (blocking all network communication) if pin TXD is forced
permanently LOW by a hardware and/or software application failure. The timer is
triggered by a negative edge on pin TXD. If the duration of the LOW-level on pin TXD
exceeds the internal timer value (tto(dom)TXD), the transmitter is disabled, driving the bus
line into a recessive state. The timer is reset by a positive edge on pin TXD.
7.10 Fail-safe features
Pin TXD provides a pull-down to GND in order to force a predefined level on input pin TXD
in case the pin TXD is unsupplied.
Pin SLP_N provides a pull-down to GND in order to force the transceiver into Sleep mode
in case the pin SLP_N is unsupplied.
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 9 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
Pin RXD is set floating in case of lost power supply on pin VBAT.
The current of the transmitter output stage is limited in order to protect the transmitter
against short circuit to pins VBAT or GND.
A loss of power (pins VBAT and GND) has no impact on the bus line and the
microcontroller. There are no reverse currents from the bus. The LIN transceiver can be
disconnected from the power supply without influencing the LIN bus.
The output driver at pin LIN is protected against overtemperature conditions. If the
junction temperature exceeds the shutdown junction temperature Tj(sd), the thermal
protection circuit disables the output driver. The driver is enabled again when the junction
temperature has dropped below Tj(sd) and a recessive level is present at pin TXD.
If VBAT drops below Vth(VBATL)L, a protection circuit disables the output driver. The driver is
enabled again when VBAT >V
th(VBATL)H and a recessive level is present at pin TXD.
Fig 4. Remote wake-up behavior
001aae071
LIN recessive
LIN dominant
sleep mode standby mode
0.4V
BAT
0.6V
BAT
ground
V
BAT
V
LIN
t
dom(LIN)
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 10 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
8. Limiting values
[1] Equivalent to discharging a 150 pF capacitor through a 330 resistor; verified by an external test house.
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.
[3] Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.
[4] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj=T
amb +PRth(j-a), where Rth(j-a) is a fixed value.
The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
9. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND; unless
otherwise specified. Positive currents flow into the IC.
Symbol Parameter Conditions Min Max Unit
VBAT battery supply voltage with respect to GND 0.3 +40 V
VTXD voltage on pin TXD ITXD no limitation 0.3 +6 V
ITXD < 500 A0.3 +7 V
VRXD voltage on pin RXD IRXD no limitation 0.3 +6 V
IRXD < 500 A0.3 +7 V
VSLP_N voltage on pin SLP_N ISLP_N no limitation 0.3 +6 V
ISLP_N < 500 A0.3 +7 V
VLIN voltage on pin LIN with respect to GND, VBAT and VWAKE_N 40 +40 V
VWAKE_N voltage on pin WAKE_N 0.3 +40 V
IWAKE_N current on pin WAKE_N only relevant if VWAKE_N <V
GND 0.3
current will flow into pin GND
15 - mA
VINH voltage on pin INH 0.3 VBAT +0.3 V
IO(INH) output current on pin INH 50 +15 mA
VESD electrostatic discharge voltage
according to IEC 61000-4-2 on pins WAKE_N, LIN and VBAT [1] 6+6 kV
human body model on pins WAKE_N, LIN, VBAT and INH [2] 8+8 kV
on pins RXD, SLP_N and TXD [2] 2+2 kV
charge device model all pins 750 +750 V
machine model all pins [3] 200 +200 V
Tvj virtual junction temperature [4] 40 +150 C
Tstg storage temperature 55 +150 C
Table 6. Thermal characteristics
According to IEC 60747-1.
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient SO8 package; in free air 145 K/W
HVSON8 package; in free air 50 K/W
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 11 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
10. Static characteristics
Table 7. Static characteristics
VBAT = 5.5 V to 27 V; Tvj =
40
C to +150
C; RL(LIN-VBAT) = 500
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
IBAT battery supply current Sleep mode
VLIN =V
BAT;V
WAKE_N =V
BAT
VTXD =0V; V
SLP_N =0V
2710A
Standby mode; bus recessive
VINH =V
BAT; VLIN =V
BAT
VWAKE_N =V
BAT; VTXD =0V
VSLP_N =0V
150 450 1000 A
Standby mode; bus dominant
VBAT =12V; V
INH =12V
VLIN =0V; V
WAKE_N =12V
VTXD =0V V
SLP_N =0V
300 800 1200 A
Normal mode; bus recessive
VINH =V
BAT; VLIN =V
BAT
VWAKE_N =V
BAT; VTXD =5V
VSLP_N =5V
300 800 1600 A
Normal mode; bus dominant
VBAT =12V; V
INH =12V
VWAKE_N =12V; V
TXD =0V
VSLP_N =5V
124mA
Power-on reset
Vth(POR)L LOW-level power-on reset
threshold voltage
power-on reset 1.6 3.1 3.9 V
Vth(POR)H HIGH-level power-on reset
threshold voltage
2.3 3.4 4.3 V
Vhys(POR) power-on reset hysteresis
voltage
0.05 0.3 1 V
Vth(VBATL)L LOW-level VBAT LOW
threshold voltage
3.9 4.4 4.7 V
Vth(VBATL)H HIGH-level VBAT LOW
threshold voltage
4.2 4.7 4.9 V
Vhys(VBATL) VBAT LOW hysteresis
voltage
0.05 0.3 1 V
Pin TXD
VIH HIGH-level input voltage 2 - 7 V
VIL LOW-level input voltage 0.3 - +0.8 V
Vhys hysteresis voltage 50 200 400 mV
RPD(TXD) pull-down resistance on pin
TXD
VTXD = 5 V 140 500 1200 k
IIL LOW-level input current VTXD =0 V 5-+5A
IOL LOW-level output current local wake-up request
Standby mode; VWAKE_N =0V
VLIN =V
BAT; VTXD =0.4V
1.5 - - mA
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 12 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
Pin SLP_N
VIH HIGH-level input voltage 2 - 7 V
VIL LOW-level input voltage 0.3 - +0.8 V
Vhys hysteresis voltage 50 200 400 mV
RPD(SLP_N) pull-down resistance on pin
SLP_N
VSLP_N = 5 V 140 500 1200 k
IIL LOW-level input current VSLP_N =0V 50+5A
Pin RXD (open-drain)
IOL LOW-level output current Normal mode
VLIN =0V;V
RXD =0.4V
1.5 - - mA
ILH HIGH-level leakage current Normal mode
VLIN =V
BAT;V
RXD =5V
50+5A
Pin WAKE_N
VIH HIGH-level input voltage VBAT 1- V
BAT +0.3 V
VIL LOW-level input voltage 0.3 - VBAT 3.3 V
Ipu(L) LOW-level pull-up current VWAKE_N =0V 30 12 1A
ILH HIGH-level leakage current VWAKE_N =27V; V
BAT =27V 50+5A
Pin INH
Rsw(VBAT-INH) switch-on resistance
between pins VBAT and INH
Standby; Normal and Power-on
modes; IINH =15 mA
VBAT =12V
-2050
ILH HIGH-level leakage current Sleep mode
VINH =27V; V
BAT =27V
50+5A
Pin LIN
IBUS_LIM current limitation for driver
dominant state
VBAT =18V; V
LIN =18V
VTXD =0V
40 - 100 mA
Rpu pull-up resistance Sleep mode; VSLP_N = 0 V 50 160 250 k
IBUS_PAS_rec receiver recessive input
leakage current
VLIN = 27 V; VBAT =5.5V
VTXD =5V
--1A
IBUS_PAS_dom receiver dominant input
leakage current including
pull-up resistor
Normal mode; VTXD =5V
VLIN =0V; V
BAT = 12 V
600 - - A
VSerDiode voltage drop at the serial
diode
in pull-up path with Rslave
ISerDiode =10A
[2] 0.4 - 1.0 V
IBUS_NO_GND loss-of-ground bus current VBAT =27V; V
LIN =0V 750 - +10 A
IBUS_NO_BAT loss-of-battery bus current VBAT =0V; V
LIN =27V - - 1 A
VBUSdom receiver dominant state - - 0.4VBAT V
VBUSrec receiver recessive state 0.6VBAT -- V
VBUS_CNT receiver center voltage VBUS_CNT =
(VBUSrec +V
BUSdom)/2
0.475VBAT 0.5VBAT 0.525VBAT V
VHYS receiver hysteresis voltage VHYS = VBUSrec VBUSdom - - 0.175VBAT V
Rslave slave resistance connected between pins LIN and
VBAT; VLIN =0V; V
BAT =12V
20 30 47 k
Table 7. Static characteristics …continued
VBAT = 5.5 V to 27 V; Tvj =
40
C to +150
C; RL(LIN-VBAT) = 500
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
see Figure 6
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 13 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Not tested in production; guaranteed by design.
11. Dynamic characteristics
CLIN capacitance on pin LIN [2] - - 30 pF
Vo(dom) dominant output voltage Normal mode; VTXD = 0 V
VBAT =7.0V
--1.4V
Normal mode; VTXD = 0 V
VBAT =18V
--2.0V
Thermal shutdown
Tj(sd) shutdown junction
temperature
[2] 150 175 200 C
Table 7. Static characteristics …continued
VBAT = 5.5 V to 27 V; Tvj =
40
C to +150
C; RL(LIN-VBAT) = 500
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Dynamic characteristics
VBAT = 5.5 V to 18 V; Tvj =
40
C to +150
C; RL(LIN-VBAT) = 500
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
Duty cycles
1 duty cycle 1 Vth(rec)(max) = 0.744 VBAT
Vth(dom)(max) = 0.581 VBAT
tbit =50s; VBAT =7Vto18V
[2][3][4][7] 0.396 - -
Vth(rec)(max) =0.76 VBAT
Vth(dom)(max) = 0.593 VBAT
tbit =50s; VBAT = 5.5 V to 7.0 V
[2][3][4][7] 0.396 - -
2 duty cycle 2 Vth(rec)(min) = 0.422 VBAT
Vth(dom)(min) = 0.284 VBAT
tbit =50s; VBAT =7.6Vto18V
[2][4][5][7] --0.581
Vth(rec)(min) = 0.41 VBAT
Vth(dom)(min) = 0.275 VBAT
tbit =50s; VBAT = 6.1 V to 7.6 V
[2][4][5][7] --0.581
3 duty cycle 3 Vth(rec)(max) = 0.778 VBAT
Vth(dom)(max) = 0.616 VBAT
tbit =96s; VBAT =7Vto18V
[3][4][7] 0.417 - -
Vth(rec)(max) = 0.797 VBAT
Vth(dom)(max) = 0.630 VBAT
tbit =96s; VBAT =5.5Vto7V
[3][4][7] 0.417 - -
4 duty cycle 4 Vth(rec)(min) = 0.389 VBAT
Vth(dom)(min) = 0.251 VBAT
tbit =96s; VBAT =7.6Vto18V
[4][5][7] --0.590
Vth(rec)(min) = 0.378 VBAT
Vth(dom)(min) = 0.242 VBAT
tbit =96s; VBAT = 6.1 V to 7.6 V
[4][5][7] --0.590
Timing characteristics
tffall time [2][4] - - 22.5 s
see Figure 6
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 14 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Not applicable for the /10 versions of the TJA1021.
[3] . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 6.
[4] Bus load conditions are: CBUS = 1 nF and RBUS =1k; CBUS = 6.8 nF and RBUS =660; CBUS = 10 nF and RBUS = 500 .
[5] . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 6.
[6] Load condition pin RXD: CRXD = 20 pF and RRXD =2.4k.
[7] For VBAT > 18 V the LIN transmitter might be suppressed. If TXD is HIGH then the LIN transmitter output is recessive.
trrise time [2][4] - - 22.5 s
t(r-f) difference between rise
and fall time
VBAT = 7.3 V [2][4] 5- +5s
ttx_pd transmitter propagation
delay
rising and falling [2] --6s
ttx_sym transmitter propagation
delay symmetry
[2] 2.5 - +2.5 s
trx_pd receiver propagation
delay
rising and falling [6] --6s
trx_sym receiver propagation
delay symmetry
[6] 2- +2s
twake(dom)LIN LIN dominant wake-up
time
Sleep mode 30 80 150 s
twake(dom)WAKE_N dominant wake-up time
on pin WAKE_N
Sleep mode 7 30 50 s
tgotonorm go to normal time time period for mode change from
Sleep, Power-on or Standby mode
into Normal mode
2510s
tinit(norm) normal mode
initialization time
5- 20s
tgotosleep go to sleep time time period for mode change from
Normal slope mode into Sleep mode
2510s
tto(dom)TXD TXD dominant time-out
time
VTXD = 0 V 27 55 90 ms
Table 8. Dynamic characteristics …continued
VBAT = 5.5 V to 18 V; Tvj =
40
C to +150
C; RL(LIN-VBAT) = 500
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
13
tbus recmin
2t
bit
-------------------------------
=
aaaaaaaa
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 15 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
Fig 5. Timing test circuit for LIN transceiver
001aae069
GND
WAKE_N
SLP_N
TXD
RXD LIN
INH
VBAT
TJA1021
RRXD
RL
100 nF
CRXD CL
Fig 6. Timing diagram LIN transceiver
015aaa245
VTXD
receiving
node 1
receiving
node 2
VRXD
VRXD
tbit
tbus(dom)(max) tbus(rec)(min)
Vth(rec)(max) thresholds of
receiving node 1
Vth(dom)(max)
Vth(rec)(min)
Vth(dom)(min)
tbus(dom)(min)
trx_pdr
trx_pdf
trx_pdr tprx_pdf
tbus(rec)(max)
tbit tbit
thresholds of
receiving node 2
VBAT LIN BUS
signal
BAWERY 001832070
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 16 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
12. Application information
13. Test information
Immunity against automotive transients (malfunction and damage) in accordance with LIN
EMC Test Specification / Version 1.0; August 1, 2004.
The waveforms of the applied transients are according to ISO 7637-2: Draft 2002-12, test
pulses 1, 2a, 3a and 3b.
13.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC)
standard Q100 or Q101 and is suitable for use in automotive applications.
(1) Typically specified by car manufacturer, e.g. master: C = 1 nF; slave: C = 220 pF.
Fig 7. Typical application of the TJA1021
001aae070
1 kΩ
WAKE_N
VBAT
INH
LIN BUS
LINE
ECU
only for
master node
LIN
(1)
87
5
1
4
26
3
TJA1021
VDD
GND
TX0
Px.x
RX0
TXD
SLP_N
RXD
MICRO-
CONTROLLER
BATTERY
+5 V/
+3.3 V
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 17 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
14. Package outline
Fig 8. Package outline SOT96-1 (SO8)
UNIT A
max. A
1 A
2 A
3 b
p c D
(1) E
(2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1 0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15 0.05 0.244
0.228
0.028
0.024
0.028
0.012
0.01 0.01 0.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18
I —\ /‘ c 4 ¥ ? L’SLDA , |:| ‘ VAN—1 pg“ “ rm E© W
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 18 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
Fig 9. Package outline SOT782-1 (HVSON8)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT782-1 - - -
- - -
sot782-1_po
09-08-25
09-08-28
Unit(1)
mm
max
nom
min
1.00
0.85
0.80
0.05
0.03
0.00
0.2
3.10
3.00
2.90
2.45
2.40
2.35
3.10
3.00
2.90
0.65 1.95
0.45
0.40
0.35
0.1
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 maximum per side are not included.
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm SOT782-1
A1b
0.35
0.30
0.25
cDD
hEE
h
1.65
1.60
1.55
ee
1K
0.35
0.30
0.25
Lv
0.1
w
0.05
y
0.05
y1
012 mm
scale
MO-229
X
C
y
C
y1
detail X
A
c
A1
B A
D
E
terminal 1
index area
b
Dh
L
Eh
K
e1
eAC B
v
Cw
1 4
8 5
terminal 1
index area
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 19 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
Figure 10 Table 9 10 Figure 10
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 20 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
Table 9. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 10. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
maxmum peak |emperature I = MSL Imm damage \evel mwmmum peak lempevature = mwmum so‘denng lempevature Semion 16
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 21 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
•AN10365 ‘Surface mount reflow soldering description”
•AN10366 “HVQFN application information”
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Se on 2.1 Figure 2 Section 7 Table 8 Table note 2 Figure 7 Figure note 1
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 22 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
18. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1021 v.8 20181218 Product data sheet - TJA1021 v.7
Modifications: •ISO 17987-4:2016 (12 V) compliant
•Section 2.1: pin-to-pin compatible with MC33662
•Figure 2(b): revised/resized
•Section 7: 2nd paragraph added
•Table 8, Table note 2: table note reference added to parameter ttx_sym
•Figure 7, Figure note 1 revised
TJA1021 v.7 20110325 Product data sheet - TJA1021 v.6
TJA1021 v.6 20101230 Product data sheet - TJA1021 v.5
TJA1021 v.5 20091022 Product data sheet - TJA1021 v.4
TJA1021 v.4 20090119 Product data sheet - TJA1021 v.3
TJA1021 v.3 20071008 Product data sheet - TJA1021 v.2
TJA1021 v.2 20070903 Preliminary data sheet - TJA1021 v.1
TJA1021 v.1 20061016 Objective data sheet - -
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 23 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
httg:llwww.nxg.com salesaddressesangcom
TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 8 — 18 December 2018 24 of 25
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors TJA1021
ISO 17987/LIN 2.x/SAE J2602 transceiver
© NXP B.V. 2018. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 December 2018
Document identifier: TJA1021
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Low power management . . . . . . . . . . . . . . . . . 1
2.3 Protection mechanisms . . . . . . . . . . . . . . . . . . 2
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
7.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.5 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.6 Remote and local wake-up . . . . . . . . . . . . . . . . 8
7.7 Wake-up via mode transition . . . . . . . . . . . . . . 8
7.8 Wake-up source recognition . . . . . . . . . . . . . . . 8
7.9 TXD dominant time-out function . . . . . . . . . . . . 8
7.10 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 8
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
9 Thermal characteristics . . . . . . . . . . . . . . . . . 10
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13
12 Application information. . . . . . . . . . . . . . . . . . 16
13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16
13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 16
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Handling information. . . . . . . . . . . . . . . . . . . . 19
16 Soldering of SMD packages . . . . . . . . . . . . . . 19
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 19
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 19
16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20
17 Soldering of HVSON packages. . . . . . . . . . . . 21
18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
20 Contact information. . . . . . . . . . . . . . . . . . . . . 24
21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Products related to this Datasheet

IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER FULL 1/1 8HVSON
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER FULL 1/1 8SO
IC TRANSCEIVER 1/1 8SO